Field of the Invention
The present invention relates to an integrated circuit device and a configuration method thereof.
Description of the Related Art
As a technique of stacking a plurality of semiconductor integrated circuit chips to increase the packaging density of semiconductor integrated circuit chips, for example, techniques called PoP (Package on Package) and CoC (Chip on Chip) have already been put into practical use. However, in conventional PoP or CoC, general means such as a bonding wire and interposer are used to connect semiconductor integrated circuit chips to each other. The parasitic capacitances of these means hinder a high-speed operation.
To solve this problem, a technique called TSV (Through Silicon Via) using wiring and electrodes which penetrate the inside of chips is proposed as another technique of connecting stacked semiconductor integrated circuit chips to each other (see, for example, Japanese Patent Laid-Open No. 2010-109264). By using TSV, semiconductor integrated circuit chips are connected to each other by a shortest distance. Thus, a small parasitic capacitance, high-speed operation, and low power consumption can be implemented.
In an electronic device such as a compact digital camera, a dual processor system in which two system LSI chips are mounted on a motherboard is sometimes built to improve the arithmetic processing capability. Note that a system LSI chip includes a processor such as a CPU, and a memory controller. As a temporary storage area, the system LSI chip requires a memory such as a DRAM (Dynamic Random Access Memory). To operate respective processors in parallel, memories corresponding to respective system LSI chips are necessary. As building components, the dual processor system requires, for example, two system LSI chips and two memory chips each including a memory core, that is, a total of four semiconductor integrated circuit chips.
To increase the packaging density, there is a demand to implement one stacked dual processor package in which two system LSI chips and two memory chips, that is, a total of four chips are stacked by the above-mentioned TSV technique in the dual processor system.
However, when a plurality of system LSI chips having the same structure and a plurality of memory chips having the same structure are stacked using the TSV technique, a plurality of memory controllers and a plurality of memory cores are connected to a common bus, causing bus collision. As a result, the respective memory controllers cannot access the paired memory cores in parallel, degrading the processing performance.
There is also a device which does not require so high processing performance as to mount a stacked dual processor package, and mounts a stacked single processor package in which one system LSI chip and one memory chip are stacked. In this case, it is desirable in terms of the production cost to divert common chips for a stacked dual processor package and stacked single processor package.